Of Thee I Sing

The musical lampoons American politics; the story concerns John P. Wintergreen, who runs for President of the United States on the love platform. When he falls in love with the sensible Mary Turner instead of Diana Devereaux, the beautiful pageant winner selected for him, he gets into political hot water. https://en.wikipedia.org/wiki/Of_Thee_I_Singhttps://digitalcommons.otterbein.edu/summer_production_1976/1001/thumbnail.jp

Maine Campus November 21 1997

A fully integrated 265Vrms input AC-DC interface is demonstrated in a 0.35um CMOS technology, needing only 1 external low voltage SMD capacitor for improved performance. The converter can directly interface the universal line voltage (50-60Hz) and converts this into a regulated DC voltage of 3.3V. High input voltage operation is made possible through custom layout of high voltage capable passive components. A model of an ideal AC-DC capacitive step-down converter is presented and the proposed circuit architecture is designed to approach maximum attainable power throughput. The prototype converter demonstrates a maximum output power of 287uW on a die area of 6mm2 and enables integrated circuits to be supplied straight from the ubiquitus mains voltage. Hereby circumventing the need for traditional converters using high voltage discrete components.status: publishe

Low-power, 10-Gbps 1.5-Vpp differential CMOS driver for a silicon electro-optic ring modulator

We present a novel driver circuit enabling electro-optic modulation with high extinction ratio from a co-designed silicon ring modulator. The driver circuit provides an asymmetric differential output at 10Gbps with a voltage swing up to 1.5V(pp) from a single 1.0V supply, maximizing the resonance-wavelength shift of depletion-type ring modulators while avoiding carrier injection. A test chip containing 4 reconfigurable driver circuits was fabricated in 40nm CMOS technology. The measured energy consumption for driving a 100fF capacitive load at 10Gbps was as low as 125fJ/bit and 220fJ/bit at 1V(pp) and 1.5V(pp) respectively. After flip-chip integration with ring modulators on a silicon-photonics chip, the power consumption was measured to be 210fJ/bit and 350fJ/bit respectively

A 94.6%-Efficiency Fully Integrated Switched-Capacitor DC-DC Converter in Baseline 40nm CMOS Using Scalable Parasitic Charge Redistribution

© 2016 IEEE. In recent years, there has been an ever-increasing interest in monolithic power supplies. Integrating the power supply with the application has many direct benefits, including a reduction of the bill of materials and reduced size. Even more substantial are the potential efficiency gains due to reduced power delivery network losses and voltage margins, especially in a world dominated by energy limited devices where this translates directly into improved battery life. However, to warrant a migration to integrated power supplies, it is crucial that these gains do not get eclipsed by the decreased efficiency of the power converter caused by the reduced quality of integrated passives. Switched-Capacitor (SC) converters have become more and more popular because, contrary to inductive converters, they only use transistors and capacitors, both of which are native to CMOS technologies and scale well into deep-submicron nodes. The maximal efficiency of an SC converter depends on two factors [1]: a topological parameter whose optimal value depends on the Voltage Conversion Ratio (VCR), and a, the relative size of the parasitic, so-called Bottom-Plate (BP), capacitance to the flying capacitance. The further the VCR is removed from 1/1 and the larger a, the lower the efficiency that is obtained. With a typically around 1.5% for MOM- and MIM-, and 7% for MOS capacitors, an SC converter could theoretically achieve an efficiency of 89% and 79% respectively for a 1/2 conversion [1]. Due to additional losses (control, leakage, etc.), this efficiency ceiling is lower, but its existence is still confirmed by previous work. The highest reported monolithic SC converter efficiencies in baseline CMOS are 87% [2], although at a more favorable VCR of 4/5, and 85% [3], both using MIM capacitors. Higher efficiencies have been demonstrated using high-density Deep-Trench (90%) [4] or Ferro-Electric (91% in 1/2) [5] capacitors, which have reportedly up to 25 times smaller α. However, these capacitors are not part of baseline CMOS and thus require additional masks and costs.status: publishe

Fully Integrated Wide Input Voltage Range Capacitive DC-DC Converters: The Folding Dickson Converter

This paper presents a modified Dickson converter to achieve wide input range capacitive DC-DC converters. Several implementations are carefully studied and compared, which shows that the folding Dickson converter is the best choice, not only for its reduced dynamic losses, but also for its very regular structure and operation. Folding is achieved by merging the terminals of two or more flying capacitors, creating one equivalent flying capacitor. In this design, a four stage folding Dickson converter is implemented to achieve four different voltage conversion ratios. A Bootstrapped Gate Boost Converter (BGBC) is proposed which uses a bootstrapping technique to generate a floating rail for the flying switches, whose terminal voltages vary by large amounts depending on input voltage and VCR. The inherent operation of the Dickson topology is used by copying the voltage of the flying capacitors on a grounded capacitor in one phase, which can then be used to generate a floating 1.2V in the second phase. The converter has been implemented in a 90nm technology, achieving a maximum output power of 50mW, peak efficiency of 76.6% in the 2:1 conversion mode, and an average efficiency above 60% over the entire Vin and Pout range.status: publishe

Scalable Parasitic Charge Redistribution: Design of High-Efficiency Fully Integrated Switched-Capacitor DC-DC Converters

This paper introduces a technique, called scalable parasitic charge redistribution (SPCR), that reduces the parasitic bottom-plate losses in fully integrated switched-capacitor (SC) voltage regulators up to any desired level. This is realized by continuously redistributing the parasitic charge in-between phase-shifted converter cores. Because earlier models described the ratio of this parasitic coupling to the flying capacitance as the only limiting factor on the achievable fully integrated efficiency, the use of SPCR allows SC converters to achieve efficiencies previously deemed impossible. Transistor leakage is shown to be another limiting factor and is added to existing models which are then used to prove the effectiveness of SPCR over a wide range of power densities (up to 10 W/mm2) and technological parameters. The implementation of SPCR requires little overhead thanks to the use of charge redistribution buses. A 1/2 converter is fabricated in a 40 nm bulk CMOS technology that demonstrates SPCR by achieving a record efficiency for fully integrated closed-loop SC converters of 94.6%.status: publishe

High-ratio Voltage Conversion in CMOS for Efficient Mains-connected Standby

The focus of this work can be seen as making the bridge between the fields of Solid-State Integrated Circuits (IC) and Power Electronics. Multiple AC-DC and DC-DC power converters are investigated from the IC standpoint, this means a constant effort to realize converters that are fully integrated on a single chip, or have at least a very high level of integration. Moreover, it is of paramount importance to improve power conversion efficiency throughout the transport chain of energy from source (e.g., a battery, the mains) to load (i.e., the application which is the consumer). Creating new converter systems that are very efficient and integrated into chip-scale solutions enable the benefit of longer battery autonomy in portable devices, on top of enabling ever lighter and slimmer devices. In non-mobile applications, less power is required from the mains for the same functionality and consequently this helps to reduce emissions related to electricity generation, such as carbon dioxide, etc. To summarize this work, a few different research targets are introduced: 1) monolithic switched-capacitor DC-DC conversion for granular power delivery on-chip, 2) reduction of standby power in mains-connected devices through the addition of an efficient and compact auxiliary supply to provide power during standby mode, and 3) high-ratio DC-DC voltage conversion in a monolithic context. Modern integrated circuits contain more and more functionality within a single chip. These are also called Systems on Chip and examples of such systems are the Application Processing Unit chips at the heart of today’s smartphones or personal computers. Because these single-chip systems house a large amount of subsystems, it is only logical that they require multiple different supply voltages to power these functions. In the past, most required voltages were generated off-chip on the printed circuit board, in the vicinity of the chip. This approach, however, is becoming less and less viable due the growing number of desired supply voltages and the associated number of interconnection pins to get the power from the off-chip power converters to the on-chip loads. Moreover, there are other negative aspects related to this approach. Therefore, a better approach is to provide the chip with one, or a few, different supply voltages, and use on-chip power converters to further provide the desired supply voltages. This requires less package pins, and enables better regulation of the desired supply voltage, since the feedback loop can now be performed locally on the chip. The goal of this work is to enable the above. To that end, an investigation of suitable fully-integrated DC-DC converters is conducted. Specifically, the realization of a switched-capacitor DC-DC converter in a standard CMOS technology with a high power density was targeted. It is important to implement the converter in a standard CMOS process to enable co-integration with its loading circuits on the same chip. Secondly, a high power conversion density yields a lower chip area requirement to implement the converter. This work investigated circuit techniques to deliver top-notch specifications, given this context. Standby power is caused by mains-connected devices in standby mode. They have a power supply that is optimized for the active mode, where power levels may be very large with respect to the low required power level of standby, a factor 100x or more. It cannot be expected that these converters are efficient both at their nominal power (active mode) and also at light-load (standby mode) condition. Therefore, the power consumption of mains-connected devices is much higher than what it could be. Since standby power on a global scale is associated to about 10% of residential electricity consumption and 1% of CO2 emissions, standby power reduction could help to counter global warming. Therefore, this work aims to build the AC-DC converters that enable such reductions in standby power and prevent the associated emissions. The research toward high-ratio voltage conversion in an integrated context is motivated by the research conclusion, of the previous work on AC-DC converters, that switched-capacitor DC-DC converters are particularly well suited for this task. Monolithic high-ratio DC-DC conversion can, for example, be used to deliver high voltages from a standard Li-ion battery in a very small and light form factor, which is particularly important for robotic insects, where high voltages are required in the drivers that power the wings. Switched-capacitor DC-DC converters do not rely on the duty cycle to set their voltage conversion ratio, as its popular inductive buck converter counterpart does, and can therefore maintain a 50% duty cycle, regardless of the actual voltage conversion ratio. Instead, the conversion ratio is a consequence of the switched-capacitor topology. As such, it is a better candidate for high-ratio voltage conversion than the buck converter, which is this case more affected by efficiency limiting drawbacks, due to its reliance on very low duty cycles in order to obtain high voltage conversion ratios. The research in this work explores, given the system-level choice for the SC DC-DC converter, which topology is expected to yield the best performance, considering the typical context of CMOS integration.Contents Voorwoord i Abstract v Samenvatting vii Contents ix List of abbreviations xv List of symbols xvii 1 Introduction 1 1.1 Standby energy consumption . . . . . . . . . . . . . . . . . . . 2 1.1.1 Origin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.1.2 Quantifying standby power . . . . . . . . . . . . . . . . 2 1.1.3 Future trend . . . . . . . . . . . . . . . . . . . . . . . . 4 1.2 Auxiliary low-power converter for high efficiency in standby . . 4 1.3 Recent evolution of power management circuits . . . . . . . . . 6 1.3.1 From discrete to fully integrated . . . . . . . . . . . . . 6 1.3.2 From centralized to granularized . . . . . . . . . . . . . 9 1.4 Dissertation outline . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 Switched-capacitor DC-DC in bulk CMOS for on-chip power granularization 13 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2 Topology of a 2:1 step-down switched-capacitor DC-DC converter 15 2.2.1 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3 Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3.1 CMOS integration difficulties . . . . . . . . . . . . . . . 20 2.3.2 Flying-Well technique . . . . . . . . . . . . . . . . . . . 20 2.3.3 Intrinsic-Charge-Recycling technique . . . . . . . . . . . 22 2.3.4 Multi-phase time interleaving . . . . . . . . . . . . . . . 31 2.3.5 Avoiding multi-phase time interleaving . . . . . . . . . . 32 2.4 Converter design and optimization . . . . . . . . . . . . . . . . 33 2.5 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.6 Experimental verification . . . . . . . . . . . . . . . . . . . . . 39 2.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 3 Toward monolithic integration of mains interfaces 47 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.3 Target functionality and specification . . . . . . . . . . . . . . . 50 3.4 Research challenges . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.5 Bridging the voltage gap . . . . . . . . . . . . . . . . . . . . . . 54 3.5.1 Single-stage approach . . . . . . . . . . . . . . . . . . . 54 3.5.2 Two-stage approach . . . . . . . . . . . . . . . . . . . . 54 3.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 4 A single-stage monolithic mains interface in 0.35 μm CMOS 57 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 4.2 High-input-voltage architectures . . . . . . . . . . . . . . . . . 59 4.3 Proposed system architecture and operation . . . . . . . . . . . 62 4.3.1 Capacitive AC-DC step-down . . . . . . . . . . . . . . . 64 4.3.2 Shunt overvoltage protection and series regulation . . . 64 4.4 Converter model . . . . . . . . . . . . . . . . . . . . . . . . . . 65 4.5 Implementation in CMOS . . . . . . . . . . . . . . . . . . . . . 68 4.5.1 High-voltage passive components . . . . . . . . . . . . . 68 4.5.2 Regulation circuits . . . . . . . . . . . . . . . . . . . . . 70 4.6 Chip measurements . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 5 Two-stage approach for compact and efficient low power from the mains 77 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 5.2 Subdivision of the voltage processor . . . . . . . . . . . . . . . 78 5.2.1 Synergy through cascading . . . . . . . . . . . . . . . . 78 5.2.2 Considering the low-power mains-connected context . . 79 5.2.3 Design choice overview . . . . . . . . . . . . . . . . . . . 80 5.2.4 Primary converter . . . . . . . . . . . . . . . . . . . . . 83 5.2.5 Secondary converter: high-efficiency and high-ratio DC- DC voltage conversion . . . . . . . . . . . . . . . . . . . 86 5.2.6 Summary of system considerations from full-system point of view . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 5.3 Searching for switched-capacitor converter topology candidates 89 5.3.1 Topology trends : regularity vs irregularity . . . . . . . 89 5.3.2 Switched-capacitor topology construction . . . . . . . . 91 5.3.3 Switched-capacitor topology survey . . . . . . . . . . . . 93 5.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6 An 11/1 switched-capacitor DC-DC converter for low power from the mains 97 6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 6.2 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.3 System overview and operation . . . . . . . . . . . . . . . . . . 99 6.3.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . 99 6.3.2 11/1 power plant . . . . . . . . . . . . . . . . . . . . . . 102 6.3.3 Power-switch driver construction and operation . . . . . 103 6.3.4 Auxiliary rail generation . . . . . . . . . . . . . . . . . . 106 6.3.5 Control system . . . . . . . . . . . . . . . . . . . . . . . 107 6.4 Chip implementation and measurements . . . . . . . . . . . . . 110 6.4.1 Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . 112 6.4.2 Load regulation . . . . . . . . . . . . . . . . . . . . . . . 114 6.4.3 Line regulation . . . . . . . . . . . . . . . . . . . . . . . 115 6.4.4 Comparison . . . . . . . . . . . . . . . . . . . . . . . . . 117 6.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 7 Monolithic SC DC-DC toward even higher voltage conversion ratios 121 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 7.2 Motivation and target . . . . . . . . . . . . . . . . . . . . . . . 123 7.3 Impact of CMOS integration and topology comparison parameters124 7.3.1 Integrated capacitors . . . . . . . . . . . . . . . . . . . . 124 7.3.2 Integrated switches . . . . . . . . . . . . . . . . . . . . . 127 7.3.3 Topology comparison parameters . . . . . . . . . . . . . 128 7.4 Topology comparison . . . . . . . . . . . . . . . . . . . . . . . . 129 7.5 The difference between theory and practice . . . . . . . . . . . 132 7.6 Simulation results for Dickson Star topology . . . . . . . . . . . 134 7.7 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 8 Conclusions and future work 139 8.1 Overview and conclusions . . . . . . . . . . . . . . . . . . . . . 139 8.2 Main contributions . . . . . . . . . . . . . . . . . . . . . . . . . 141 8.3 Future work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 8.3.1 Fundamental concepts . . . . . . . . . . . . . . . . . . . 142 8.3.2 Application concepts . . . . . . . . . . . . . . . . . . . . 144 A Topology survey data 147 Bibliography 159 Biography 169 List of publications 171nrpages: 198status: publishe

Monolithic Integration of a Class DE Inverter for On-Chip Resonant DC-DC converters

A fully-integrated series resonant class DE inverter is realized in a 130 nm 1.2 V CMOS technology with an on-chip spiral inductor and an integrated MIMcap. It is used as the first stage in fully-integrated class DE DC-DC resonant converters. The inherent soft switching yields high conversion efficiency at high switching frequencies. Low switching peak-voltages are present in the circuit, alleviating the need for on-chip high-voltage techniques. The use of on-chip passives reduces the bill of materials (BOM) considerably. The maximum output power of the series resonant class DE inverter is 11.6 mW. The maximum power efficiency is 65.2 %. The measurement results confirm and improve previous simulations.status: publishe

A stacked full-bridge topology for high voltage DC-AC conversion in standard CMOS technology

A monolithic DC-AC converter is realized in a 130 nm 1.2V CMOS technology using a Class-D half-bridge topology. Several dies are combined to achieve a full-bridge topology, realizing a bipolar output voltage. Using a stacking technique, this output voltage can be increased. This yields AC output voltages up to 4V, which is more than three times the nominal 1.2V supply voltage of the technology. The passives are integrated on-chip. Consequently, the bill of materials (BOM) is heavily reduced. In a standard half-bridge topology, bulky external capacitors are needed to filter out the DC offset. This main obstacle of an off-chip capacitor is alleviated in the full-bridge topology, reducing the BOM even more. An output peak-to-peak voltage of 3.8V is achieved at a maximal efficiency of 58.3%. A total output power of 56mW is obtained. © 2013 IEEE.status: publishe